2+ day, 5+ hour ago   (454+ words) 12-inch high-NA EUV masks; Arm’s edge AI push; Amkor’s expansion; 3D memory; FeRAM startup makes waves; Qualcomm-AWS $60B custom silicon deal; Ayar Labs’ scale-up deal; new iPhone chip and format; rogue OpenAI agents in Germany; fab factory; fine-pitch RDL tech for advanced…...

3+ day, 13+ hour ago   (591+ words) Discrete steps are being merged with others as dimensions shrink into the angstrom range. The lines between discrete semiconductor manufacturing processes are starting to blur at sub-2nm nodes as transistors continue to shrink, sensitivity to various processes rises, and the…...

3+ day, 13+ hour ago   (202+ words) How early RTL testability analysis and DFT optimization enable shift left strategies that improve manufacturing test quality, reduce turnaround time, and deliver early quality estimates. The post Accelerating Shift Left With Early RTL DFT Analysis And Connectivity Verification appeared first…...

3+ day, 13+ hour ago   (473+ words) By Guy Cortez, Dan Alexandrescu, and Aaron Barker The semiconductor industry has invested heavily in embedded monitors to gain visibility into advanced silicon. Those monitors are essential, but the next step is not simply to collect a larger volume of…...

5+ day, 13+ hour ago   (109+ words) HBF for LLM inference; M3D SRAM with BEOL pass-gates at 2nm; distributed GPU architectures; hybrid HBM-HBF memory; GaN-on-silicon polarization superjunctions; programmable silicon photonics; Al dopant activation in 4H-SiC. The post Chip Industry Technical Paper Roundup: Sept. 8 appeared first on Semiconductor Engineering. Chip…...

1+ week, 4+ day ago   (178+ words) Multi-die design is becoming indispensable for automotive applications, such as ADAS and IVI, addressing demands for reliability and safety. The post Multi-Die Design for Automotive Applications appeared first on Semiconductor Engineering. Electronics for automobiles sit in the middle of two…...

1+ week, 5+ day ago   (98+ words) Semiconductor Engineering Chip Industry Technical Paper Roundup: Sep. 1 Wafer-scale optical interconnects for LLM training; Rowhammer-based inference attacks; 3D-IC test cases; liquid cooling for 2.5D/3D packages; wafer-scale 2D semi growth; DL-based parameter extraction for 2D transistors; and chip-placement optimization. New technical papers recently added…...

1+ week, 5+ day ago   (815+ words) Part I – Pioneering work in developing CFET-critical modules: an improved backside contact module and a novel gate stack for threshold voltage tuning. By Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi The semiconductor industry is going through a major architectural transition,…...

2+ week, 13+ hour ago   (207+ words) Researchers from Georgia Institute of Technology and Synopsys published a technical paper titled “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node.” Abstract Excerpt: The paper proposes “a monolithic-3D (M3D) 6T SRAM at the 2nm node” that integrates BEOL…...

2+ week, 2+ day ago   (173+ words) Researchers from Georgia Institute of Technology published a technical paper titled “Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation.” Abstract Excerpt: The paper analyzes “wafer-scale optical interconnects” for mixture-of-experts LLM training…...